FPGA Data Transfer Submodule
Developed a submodule for efficient data transfer from an analog front-end to an FPGA.
I worked with Vivado for the design and implementation of the module, handling hardware description, simulation, and synthesis.
| What I worked with | Details |
|---|---|
| Main Tools | Xilinx Vivado |
| Technologies | FPGA, HDL (VHDL/Verilog), Data Acquisition |
| My Role | Module Design, Implementation, Simulation |
| Impact | Enabled high-speed and reliable data transfer from analog front-end to FPGA |